The TI Wizard is a full Duplex SERDES (Serialize-Deserialize) function plus the high speed differential I/O, the built-in self test (BIST) circuitry, and the phase locked loop (PLL) and delay locked loop (DLL) circuitry needed for timing references for the SERDES. A Wizard port supports data rates from 1.0 Gbaud through 2.5 Gbaud. It also includes comma detect circuitry used for the byte alignment of incoming bit stream.
The Wizard performs basically a Fibre Channel operation: Transmit is 10-bits of 8b/1 0b encoded data in and 1 bit at 10× the frequency differential out Receive is a 10× speed serial bit stream in and 10-bit 8b/1 0b data out. The receive side also performs byte alignment. Wizard is also intended to be used as the Physical Interface Portion of the 800 Mb 1394 standard, as well as Gigabit Ethernet, board to Board interconnect, DSP test port interface, chip to chip interconnect, and any application that requires a very high speed serial interface. The primary intended application for Wizard is to provide building blocks in the ASIC library for developing point-to-point baseband data transmission over controlled impedance media of approximately 5052. The transmission media can be printed circuit boards, copper cables or fiber-optical media. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.
A Wizard port performs the data serialization, deserialization, and clock extraction functions for a physical layer interface device. The transceiver operates at a maximum of 2.5 Gbps of bandwidth over a serial interface. The transmitter portion serializes 10-bit data words at a rate based on the supplied reference clock. The 10-bit word is intended for 8b/1 0b encoded data, which is then serialized and transmitted differentially at the intended data rate using Non-Return-to-Zero (NRZ). The receive section deserializes the input data and synchronizes the 10-bit wide bus data to the local reference clock.
As shown in FIG. 1, a phase locked loop (PLL) is used for clock multiplication and a delay locked loop (DLL) is used for clock recovery. The speed of the reference clock (REFCLK) of the PLL is 100-250 MHz depending upon the ASIC or board speed of the data link. Transmit path registers the parallel data TD<0:9> at the rising edge of REFCLK, does the parallel to serial conversion and sends the serial data through the transmitter at both edges of the TX clock. Receive path receives serial data and does serial to parallel conversion using the RX clock.
One prior art structure of a time division multiplex data recovery system uses one PLL as the reference clock and two open-loop DLLs for data recovery. Although this system has the advantage of being stable in a noisy environment due to the high bandwidth of the PILL and passive DLL clock recovery, this system also has the great disadvantage of requiring high power due to use of the high speed clock which necessitates a huge clock buffer and additional digital logic processing the output of the receiver. Also disadvantageous is that the majority of the system operates digitally thus increasing the power required as the frequency of operation increases.
A second prior art system uses a single PLL for data recovery. Although this system has the advantages of operating at high speeds due to the time division multiplex of 20 slow clocks(assuming a 1:10 deserializer), low power operation due to no clock buffer requirement (clock fanout is one, i.e. capacitive load is very small) and few digital circuits in operation, and activity of all the transmitter and receivers is at a 10% duty cycle due to the time division multiplex, it also has the disadvantage of the data loop receiver having large hunting jitter and the system is not stable in noisy environments due to the extremely narrow bandwidth of operation.